1. Field of the Invention
The present invention relates to a semiconductor device, and in particular to an ESD (Electrostatic Discharge) protection circuit device incorporated in a semiconductor device in order to protect an input circuit, an output circuit, etc., of the semiconductor device from being destroyed by ESD. For example, the present invention is applied to an ESD protection circuit using an SCR (Silicon Controlled Rectifier) as a voltage clamp element for ESD protection in a CMOS LSI of low power supply voltage type.
2. Description of the Related Art
For example, in some ESD protection circuits each provided to protect an input circuit and an output circuit of an CMOS LSI from ESD destruction, diodes, transistors or SCRs are used as protection elements.
In an ESD protection circuit using an SCR, operation voltage of the SCR is typically high. In the case where the ESD protection circuit using an SCR is incorporated in a fine CMOS LSI in which the voltage of the operation power supply is made lower, therefore, a low voltage trigger needs to be made possible in order to protect MOS transistors having a low gate breakdown voltage in the CMOS LSI.
From such a background, an example in which an ESD protection circuit using an SCR is incorporated in a CMOS LSI of low power supply voltage type is disclosed in “A Gate-Coupled PTLSCR/NTLSCR ESD Protection Circuit for Deep-Submicron Low-Voltage CMOS IC's 1”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 1, JANUARY 1997.
FIG. 9 is an equivalent circuit diagram showing a principal part of an ESD protection circuit connected to an input circuit of the CMOS LSI disclosed in the above-described document. In FIG. 9, an example (conventional-art example 1) in which LVTSCRs (Low-Voltage Triggered lateral SCR) are used as the SCRs in the ESD protection circuits is shown.
In FIG. 9, a first ESD protection circuit 121 is connected between an input pad PAD connected to internal circuits and a VDD node, to which a power supply potential VDD is applied, and a second ESD protection circuit 122 is connected between the input pad PAD and ground potential VSS (GND).
In the first ESD protection circuit 121, a first SCR LVTSCR1 is connected between the VDD node and the input pad PAD at its anode and cathode, respectively. A collector-base junction of an NPN transistor Q2 is connected in parallel with a base-collector junction of a PNP transistor Q1. An emitter of the PNP transistor Q1 serves as an anode of the SCR, and an emitter of the NPN transistor Q2 serve as a cathode of the SCR.
A PMOS transistor Mp1 having a gate oxide film formed so as to become thin is connected between the VDD node and the base of the NPN transistor Q2 at its source S and drain D, respectively. A gate of the PMOS transistor Mp1 is connected to the VDD node.
A well resistor Rw1 is connected between the VDD node and a node coupled to the base of the PNP transistor Q1 and a collector (N-well) of the transistor Q2. A well resistor Rw2 is connected between the emitter of the NPN transistor Q2 and the input PAD. A substrate resistor Rsub1 is connected between the GND and a node coupled to the collector of the PNP transistor Q1 and the base (P-Sub) of the transistor Q2.
In the second ESD protection circuit 122, a second SCR LVTSCR2 is connected between the GND node and the input pad PAD at its anode and cathode, respectively. A collector-base junction of an NPN transistor Q4 is connected in parallel with a base-collector junction of a PNP transistor Q3. An emitter of the PNP transistor Q3 serves as an anode of the SCR, and an emitter of the NPN transistor Q4 serve as a cathode of the SCR.
An NMOS transistor Mn1 having a gate oxide film formed so as to become thin is connected between the base of the PNP transistor Q3 and the emitter of the NPN transistor Q4 at its drain D and source S, respectively. A gate of the NMOS transistor Mn1 is connected to the GND node.
A well resistor Rw3 is connected between the VDD node and a node coupled to the base of the PNP transistor Q3 and a collector (N-well) of the NPN transistor Q4. A substrate resistor Rsub2 is connected between the GND and the base (substrate region of NMOS transistor TN) of the NPN transistor Q4.
If a voltage equal to at least a snap-back breakdown voltage is applied to an LVTSCR2 included in the second ESD protection circuit 122 shown in FIG. 9 when a surge voltage of a positive polarity is input to the input pad PAD, then the LVTSCR2 turns on with a snap-back current serving as a base current, and a surge current is discharged to GND, thus the input gate of the input circuit is protected.
If the voltage applied to the LVTSCR2 equal to at least the snap-back breakdown voltage is higher than a gate breakdown voltage of an NMOS transistor Mn1, however, there is a problem that the internal circuits are damaged by a surge voltage input.
FIG. 10 is a circuit diagram showing a principal part of a different ESD protection circuit disclosed in the above-described document. An example (conventional-art example 2) in which low-voltage triggered lateral SCRs using a gate coupling technique are used as SCRs in the ESD protection circuits is shown.
In FIG. 10, a first ESD protection circuit 151 is the same as the first ESD protection circuit 121 shown in FIG. 9 except the following points (1) to (4). Therefore, the same components are denoted by like characters, and description thereof will be omitted.
(1) Instead of the LVTSCR1 shown in FIG. 9, a PTLSCR (PMOS-Triggered lateral SCR in which an SCR is triggerable by a PMOS transistor) is used.
(2) A PMOS transistor Mp1 is connected in parallel between the VDD node and a gate node of the PTLSCR (the base of the NPN transistor Q2) at its source and drain, respectively.
(3) A resistor element Rp is connected between the VDD node and a gate of the PMOS transistor Mp1.
(4) A capacitance element Cp is connected between the gate of the PMOS transistor Mp1 and the input pad PAD.
Similarly, a second ESD protection circuit 152 is the same as the second ESD protection circuit 122 shown in FIG. 9 except the following points (1) to (4). Therefore, the same components are denoted by like characters, and description thereof will be omitted.
(1) Instead of the LVTSCR2 shown in FIG. 9, an NTLSCR (NMOS-Triggered lateral SCR in which an SCR is triggerable by an NMOS transistor) is used.
(2) An NMOS transistor Mn1 is connected in parallel between a gate node of the NTLSCR (the base of the PNP transistor Q3) and a cathode (the emitter of the NPN transistor Q4) at its drain and source, respectively.
(3) A capacitance element Cn is connected between the input pad PAD and the gate of the NMOS transistor Mn1.
(4) A resistor element Rn is connected between a gate of the NMOS transistor Mn1 and the GND node.
When a surge voltage of a negative polarity is input to the input pad PAD in the above-described configuration, the PMOS transistor Mp1 in the first ESD protection circuit 151 using the PTLSCR transitionally turns on to give a trigger to the PTLSCR. As a result, the surge current is absorbed to the VDD node, and the input gate of the input circuit is protected. After a predetermined time based on a time constant determined by the resistor element Rp and the capacitance element Cp has elapsed, the PMOS transistor Mp1 returns to the off-state.
When a surge voltage of a positive polarity is input to the input pad PAD in the above-described configuration, the NMOS transistor Mn1 in the second ESD protection circuit 152 using the NTLSCR transitionally turns on to give a trigger to the NTLSCR. As a result, the surge current is absorbed to the GND node, and the input gate of the input circuit is protected. After a predetermined time based on a time constant determined by the resistor element Rn and the capacitance element Cn has elapsed, the NMOS transistor Mn1 returns to the off-state.
In Jpn. Pat. Appln. KOKAI Publication No. 8-321586, a technique for attaching a protection element to a common discharge line in a multi-power supply LSI is disclosed. However, it is necessary to prepare the common discharge line apart from the power supply line and the ground line. It is not favorable because a large area is occupied on an LSI chip.
In Jpn. Pat. Appln. KOKOKU Publication No. 6-5705, a technique of disposing a protection element so as to form a current path between a ground line of the circuit having a maximum area and a signal line and a power supply line.
In the convention ESD protection circuit using an SCR, however, a trigger is applied by using a transitional potential change caused when a surge voltage is input to the input pad to which SCRs are connected, and this results in a problem that favorite protection characteristics are not necessarily obtained.
In order to solve this problem, the present inventors have proposed, in Japanese Patent Application No. 2002-118253 entitled “Semiconductor device,” a semiconductor device that can implement favorable protection characteristics with a low voltage trigger and improve the reliability, in the case where an ESD protection circuit using an SCR is applied to an LSI advanced in lowering the power supply voltage.
FIG. 11 is a circuit diagram in the case where an ESD protection circuit using an SCR is applied to a CMOS LSI that is an example of a semiconductor device according to the above-described proposal.
This semiconductor device includes a first external terminal to which a first power supply voltage is supplied at the time of ordinary operation, a second external terminal and a third external terminal electrically isolated from the first external terminal, an SCR for ESD protection connected between the second external terminal and the third external terminal respectively at its anode and cathode and including a PNP transistor and an NPN transistor, and a PMOS transistor for SCR trigger connected between the second external terminal and a base of the NPN transistor respectively at its source and drain, connected to a substrate region at its source, and electrically connected to the first external terminal at its gate.
FIG. 12 is an equivalent circuit diagram showing a first ESD protection circuit taken out from the semiconductor device shown in FIG. 11.
The ESD protection circuit is connected between an input pad PAD 15 connected to an input circuit 10 of a CMOS LSI and a GND pad 14 and comprises an SCR for ESD protection. The SCR is connected between the input pad PAD 15 and the GND pad 14 at its anode and cathode thereof, respectively. A collector-base junction of an NPN transistor Q6 is connected in parallel with a base-collector junction of a PNP transistor Q5. An emitter of the PNP transistor Q5 serves as an anode of the SCR, and an emitter of the NPN transistor Q6 serve as a cathode of the SCR. A substrate resistor Rsub is connected between the base of the NPN transistor Q6 and GND.
A PMOS transistor QP for trigger input is connected between the input pad 15 and the base of the NPN transistor Q6 at its source S and drain D, respectively. A gate of the PMOS transistor QP is connected to the VDD1 pad 11. A source of the PMOS transistor QP is connected to the substrate region. A diode for reverse current absorption (D in FIG. 11), which is forward biased when the SCR is applied with a reverse voltage, is connected in parallel with the SCR.
In the circuit structure of FIG. 12, in such a state that the surge voltage input poses a problem, a normal power supply potential VDD1 is not yet applied to the VDD1 pad 11, and the gate of the PMOS transistor QP for trigger input has the ground potential.
Thus, in this state, when a surge voltage of positive polarity is input to the input pad 15, the PMOS transistor QP turns on, if a forward bias voltage greater in absolute value than a gate threshold voltage Vthp of the PMOS transistor QP is applied between the gate and source of the PMOS transistor QP. As a result, a trigger is applied to the thyristor SCR, and the thyristor SCR turns on. Thus, a surge current is discharged to the ground, and the input gate of the input circuit 10 is protected. Since the absolute value of a gate threshold voltage Vthp of a PMOS transistor QP is small, it becomes possible to start an SCR with a low voltage trigger.
FIG. 13 is a characteristic diagram schematically showing voltage-current characteristics of an SCR in the semiconductor device shown in FIG. 11.
The characteristics show how the ESD current is flown by inputting a trigger voltage lower than the breakdown voltage of an SCR in a region of at least the holding voltage of the SCR.
If the ESD protection circuit including an SCR for ESD protection and a PMOS transistor for SCR trigger as described above is incorporated, for example, between power supply pads and between signal pads in a semiconductor device using multiple power supplies, then an area occupied by a pattern of a large number of ESD protection circuits on a chip remarkably increases, resulting in an increase of the chip size.